Modem data processing systems require the rapid transfer of data between integrated circuits (“chips”). For example, a central processing unit (CPU) transfers data to the memory system, which may include a memory controller and off-chip cache. In a multi-CPU system, data may be transferred between CPUs. As CPU speeds increase, the speed of the interface between chips (bus cycle time) becomes a limiting constraint because latencies across the interfaces may exceed the system clock period.
When data is launched from one chip to another chip, it can be launched simultaneously within numerous clock/data groups. Each clock/data group consists of multiple data bits and a clock signal, each of which travels over an individual conductor. Due to process variations and varying conductor lengths, the individual bits within a clock/data group may arrive at the receiving chip at different instances. Therefore, the individual bits of data and the clock within a clock/data group must be realigned upon arrival on the receiving chip. At the receiving end, the clock/data signals can be delayed to align the signals with respect to a sampling edge of the received clock. While it is necessary to align the individual data bits within a clock/data group at the receiving end, such delays can cause jitter and other forms of distortion. In addition to causing jitter and distortion, delaying data signals can require extensive administrative overhead and additional circuitry.
To de-skew and align the received data, the data and an associated clock signal can be sent through one or more delay lines. The delayed data signals and delayed clock signals are then used to determine the amount of de-skewing and alignment needed in the received data signal. During sampling, circuitry and logic on the receiving end adjusts delay parameters (for the clock and data signals) to optimize and properly characterize the received data signal. However, there can be a problem with sampling if the delay parameters are adjusted while sampling is taking place. Glitches in sampling data can occur due to the unsteady state of the functional sampler caused by adjusting the delay parameters during sampling.
Thus, there is a need in the art for apparatus and methods that reduce the potential for data errors associated sampling in elastic interface systems. In particular, there is a need for methods and apparatuses that provide glitchless sampling from delay lines within elastic interface receiving circuits.